1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to an improved shallow trench isolation (STI) process to eliminate silicon nitride liner induced defects.
2. Description of the Prior Art
In the fabrication of semiconductor devices, isolation structures such as shallow trench isolation (STI) are formed between active areas in which electrical devices such as transistors or memory cells are to be formed. The isolation structures are formed in an early stage of the processing of a semiconductor substrate, typically prior to the formation of the transistors.
To form the STI structure, a pad oxide layer and a pad nitride layer are typically formed over the substrate surface and patterned to expose only the isolation regions, with the prospective active device regions covered. The pad nitride layer acts as a hard mask during subsequent processing steps, and the pad oxide layer functions to relieve stress between the underlying silicon substrate and the pad nitride layer.
A dry etch is then performed to form a trench through the nitride, pad oxide, and substrate. Dielectric material such as high-density plasma chemical vapor deposition (HDPCVD) oxide is then deposited to fill the trench. Thereafter, the excess dielectric material is polished away using a chemical mechanical polishing (CMP) process and the pad nitride layer is removed.
Many attempts have been made to improve the insulating quality of the STI regions formed on a semiconductor substrate. A silicon nitride liner has proven to be an effective oxygen diffusion barrier. The silicon nitride liner limits the amount of oxide that can be grown in deep trenches of DRAM arrays as well as in shallow trench structures, and as such, all but eliminates silicon crystal defects from forming within the trench capacitor array.
For example, U.S. Pat. No. 5,447,884 to Fahey, et al. discloses a process of forming shallow trench isolation with a nitride liner layer for devices in integrated circuits to solve a problem of recessing the nitride liner that led to unacceptable voids in the trench filler material by using a liner thickness of less than 5 nm.
Recent studies indicate that void defects are readily formed across the wafer at the interface between the nitride liner and the subsequently deposited trench fill layer. The void defects adversely affect the subsequent process, resulting in decreased production yield. Hitherto, there is no prior art proposing an effective solution to eliminate such problem arose from the use of a silicon nitride liner.